The present invention relates to an inverter implemented in CMOS technology, i.e., with complementary insulated-gate field-effect transistors.
DE No. A 30 08 280 corresponding to U.S. Pat. No. 4,309,665 describes an inverter comprising two transistors, namely a p-channel transistor and an n-channel transistor. The controlled current paths of the two transistors are connected in series between the positive and negative terminals of a supply-voltage source. The junction point of the controlled current paths form the inverter output. The gate of the n-channel transistor is connected to the inverter input through a first capacitor. The n-channel transistor is the output transistor of a first current mirror. The gate of the p-channel transistor is connected directly to the inverter input and through a high-value resistor to the inverter output.
In the prior art inverter, the direct-current operating points of the two transistors are set with the input signal which is capacitively coupled to the transistors. Therefore, the lower cutoff frequency is determined by the time constant of the capacitive coupling. Furthermore, after the passage of a pulse, the output of the inverter assumes the state in which its level is equal to about half the supply voltage, uless another pulse edge follows within the time determined by the time constant. The prior art inverter thus has no stable outlet level corresponding to the input signal having passed through it.